AI-Adaptive Fault Prediction on RISC-V Edge Processors Using Lightweight Hardware Counters

Abstract

Edge-class RISC-V processors increasingly operate in safety-critical and resource-limited environments where intermittent hardware faults threaten system reliability. This study proposes a co-designed AI-adaptive fault prediction framework that relies exclusively on lightweight hardware performance counters (HPCs) to enable real-time failure awareness with minimal overhead. The research aims to (1) validate the feasibility of on-device adaptive learning, (2) maintain ultra-low-latency inference, and (3) identify the most informative HPC features for early fault sensitivity under realistic class imbalance. Runtime counter traces and labeled fault logs were generated through controlled fault injection and continuous sampling. Temporal features were extracted using sliding-window buffers and normalized before training lightweight ML models compatible with TinyML constraints. The framework achieved fault inference latency of 5 ms, and adaptive learning improved classification accuracy from 85% to 95% over five incremental training rounds (+10 pp gain). Feature weight analysis showed that Cycles (0.40) and CacheMiss (0.25) provided the strongest fault discrimination, followed by BranchMis predict (0.20) and Stall events (0.15). Counter-signal behavior exhibited wider anomaly amplitude of approximately ±1.9 under fault versus ±1.1 in normal states, enabling detection sensitivity despite a 92% normal and 8% fault sample ratio. Evaluation confirms that reliable fault intelligence on RISC-V edge silicon is achievable using a minimal HPC set without cloud-heavy retraining. The study concludes that the proposed pipeline supports deployable, adaptive, and ultra-low-overhead fault prediction, improving edge processor dependability while preserving compute, memory, and latency budgets.